Field of the Invention
Defects and impurities are inherent in grown silicon crystals. Processing of the silicon introduces additional defects and impurities. Heavy metallic impurities, such as copper, gold, chromium and nickel degrade the performance of devices formed on the silicon.
One common means of reducing the effect of the metallic contaminants is through gettering. Mechanical gettering can be achieved by creating irregularities or defects at the backside of the wafer to which the metallic impurities are attracted. However, this process is not entirely satisfactory, particularly with thick wafers and low temperature processing where the gettering sites may prove to be too far from the source of the impurities. Further, high oxygen content may cause extended defects to nucleate. It is known to harness this phenomenon by intrinsic gettering which traps impurities closer to the active region of the device formed in a region denuded from defects. However, there are still major problems with respect to this gettering technique.
To overcome these problems, an alternative (extrinsic) gettering procedure has been used. This extrinsic technique involves the formation of a network of misfit dislocations along the substrate/epitaxial layer interface of the silicon. The dislocations are introduced by the controlled incorporation of germanium in the grown silicon matrix. This procedure produces dislocation arrays which are spaced from the device surface by pure, defect free silicon layers which are functionally similar to the denuded zone in intrinsic gettering.
During crystal epitaxial growth, small amounts of germanium containing gas is introduced over about 2-.mu.m thickness and is thereafter capped with pure silicon to contain the entire active region of the device (4 to 8 .mu.m). It has been found that the misfit dislocations along the silicon/silicon germanium layer interface function to getter metallic impurities away from the active region of the device.
For more information relating to extrinsic gettering by this method, the reader is referred to: "Extrinsic Gettering Via The Controlled Introduction of Misfit Dislocations," Salih et. al., Applied Physics Letter (46) (4) published Feb. 15, 1985 by the American Institute of Physics; "Extrinsic Gettering Via Epitaxial Misfit Dislocations" Vol. 133, No. 3 of the Journal of the Electrochemical Society; Electrochemical Science and Technology, March 1986; and Defect Engineering for VLSI Eptiaxial Silicon," Rozgonyi et. al., Journal Of Crystal Growth 85 (1987), pages 300 to 307.
It is also known that the switching speed of silicon bipolar devices can be increased by the introduction of heavy metallic impurities in the active region of the device. The impurities significantly reduce minority-carrier lifetime and proportionally shorten reverse recovery time. Gold and platinum impurities are often used, and are rapidly diffused into the silicon. However, because the solid solubilities of these impurities in silicon are very small, they tend to precipitate or segregate at defects, disordered regions, and surfaces. Their diffusion is therefore difficult to control and is sensitive to process conditions, particularly the diffusion temperature and time, as well as inherent and/or process induced imperfections in the silicon material.
Because of their segregation properties, large amounts of the metallic impurities must be introduced into the silicon to achieve the desired concentrations of electrically active species in the space-charge region of fast rectifiers, or the base of transistors. The electrical activity of metal precipitates is also known to be smaller than that of solutes atoms which enhance carrier generation responsible for lifetime killing. In addition, the metallic impurities nonuniformly compensate and reduce mobility, giving rise to nonuniform breakdown voltage and large forward voltage drop. Also each metallic species is associated with a fixed set of recovery characteristics, such as leakage and forward voltage drop. Combination of metal impurities to tailor recovery characteristics may be very difficult and have not been used for commercial power devices.
The present invention utilizes misfit dislocations to enhance the switching speed of power rectifiers, particularly fast recovery power rectifiers, because they produce small leakage current and are metallurgically and electrically stable, and thus, device performance does not significantly deteriortate under high power and temperature applications. Unlike processes where misfit dislocations have been previously used to remove impurities from the depletion region, in the present invention, the misfit dislocations are used to directly reduce minority carrier lifetime because they are associated with deep energy levels in the energy gap of silicon, like metallic impurities. Further, the misfit dislocations are not formed along the substrate/epitaxial layer interface as they are in the prior art extrinsic gettering technique. Instead, in the present invention, the misfit dislocations are deliberately formed within the active (depletion) region of the epitaxial layer, spaced from the interface between the epitaxial layer and the substrate. In the active region of the device, the misfit dislocations function like heavy metal impurities, thereby permitting great control over device parameters. Unlike metal impurities and structural defects formed by energetic beam irradiation, misfit dislocations are permanent defects that are not sensitive to high temperature processing short of melting the silicon material. They are also formed during the epitaxial growth and do not require additional processing steps as ones used to introduce metal impurities and structural defects. Thus, misfit dislocations provided in accordance with the present invention can be used effectively as an alternative to metal diffusion. However, the misfit dislocations can also be used as a compliment to metal diffusion to obtain significantly better results than conventional impurity introduction techniques. Flexible tailoring of recovery characteristics can be achieved by adjusting the densities of both misfit dislocations and metal impurities.
It is, therefore, a prime object of the present invention to provide a method of controlling the switching speed for bipolar power semiconductor devices, particularly fast recovery rectifiers.
It is another object of the present invention to provide a method of controlling the switching speed of bipolar power devices wherein misfit dislocations are employed directly to reduce minority carrier lifetime.
It is another object of the present invention to provide a method for controlling the switching speed for bipolar power devices through the use of misfit dislocations in the depletion region, alone or in conjunction with heavy metal diffusion.
It is another object of the present invention to tailor recovery characteristics by controllable introduction of both misfit dislocations and metal impurities.
It is another object of the present invention to provide a method for controlling the switching speed of bipolar power devices wherein one or more regions of misfit dislocations are formed in the depletion region of the device, spaced from the substrate/epitaxial layer interface of the device.
It is another object of the present invention to provide a method for controlling the switching speed of bipolar power devices wherein areas of misfit dislocations are formed along interfaces between silicon and silicon-germanium regions within the epitaxial layer.
It is another object of the present invention to provide a bipolar power device including misfit dislocations in the depletion region, spaced from the substrate/epitaxial layer interface.
In accordance with one aspect of the present invention, a method is provided for controlling the switching speed of bipolar power semiconductor devices of the type comprising a silicon substrate, an epitaxial layer comprising a silicon substrate, an epitaxial layer comprising a depletion region and a diffused layer. The method comprises the step of forming misfit dislocations in the depletion region.
The area in which the misfit dislocations are formed is spaced from the substrate/epitaxial layer interface. Preferably, the misfit dislocations are formed proximate the center of the depletion region.
The misfit dislocations forming step preferably comprises the step of forming a germanium containing layer in the depletion region in an area substantially spaced from the substrate/epitaxial layer interface. This may be accomplished by introducing germanium into the epitaxial region during epitaxy. The germanium is introduced in the range of approximately 1% to 10% by exposing the epitaxial material to a germanium containing gas as it is formed.
The misfit dislocations may be on the &lt;100&gt; plane or the &lt;111&gt; plane. The misfit dislocations are formed along the silicon/silicon germanium interface.
Multiple areas of misfit dislocations may be formed by forming a plurality of spaced germanium containing layers separated by pure silicon layers in the depletion region. The misfit dislocations will form along each silicon/silicon-germanium interface.
Metallic impurities may be introduced into the depletion region in conjunction with the formation of the misfit dislocations. Doing so enhances the concentration of the metallic impurities proximate the misfit dislocations. The misfit dislocations act as getter sites for the metallic impurities within the depletion region providing the largest concentrations of the metallic impurities in the depletion region.
In accordance with another aspect of the present invention, a bipolar power semiconductor device is provided. The device comprises a silicon substrate, an epitaxial layer comprising a depletion region and a diffused layer. An interface between the substrate and the epitaxial layer is present. Misfit dislocations are provided in the depletion region.
The area in which the misfit dislocations are formed is spaced from the substrate/epitaxial layer interface. Preferably, it is proximate the center of the depletion region.
The device further comprises germanium containing regions, having silicon/silicon-germanium interfaces, formed in the depletion region. The area of misfit dislocations is at the silicon/silicon-germanium interface. The germanium containing region preferably comprises germanium in the range of from 1% to 10%.
The device may include a plurality of areas of misfit dislocations. Each of the areas is spaced from the substrate/epitaxial layer interface. Multiple areas of misfit dislocations may be formed by a plurality of spaced germanium containing regions, each having silicon/silicon-germanium interfaces. Misfit dislocations are formed at each of the silicon/silicon-germanium interfaces.
The device may further include metallic impurities with enhanced concentration proximate the misfit dislocations. The misfit dislocations form getter sites for the metallic impurities.
To these and such other objects which may hereinafter appear, the present invention relates to a method of controlling the switching speed of bipolar power devices as set forth in detail in the following specification and recited in the annexed claims, taken together with the accompanying drawings, wherein like numerals refer to like parts and in which: